1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device having an SOI structure, and particularly to a dry etching method effective when a contact hole for a fully depleted-SOI device is defined.
2. Description of the Related Art
In recent years, attention has been given to a fully depleted-SOI device in that it can be expected to yield speeding-up and low power consumption.
In order to implement a fully depleted-SOI device having a micro or extremely small gate length, there is a need to increase the concentration of an impurity in a channel region, restrain the extension of a depletion layer from each of source and drain regions, and increase a charge share coefficient to thereby suppress a short channel effect. On the other hand, since the spread of a depletion layer placed under a gate electrode becomes narrow when the concentration of the impurity in the channel region is increased, it is necessary to thin the thickness of an SOI layer for the purpose of execution of a fully-depleted operation. When the gate length is 200 nm or less, the thickness of the SOI layer must be thinned to 20 nm to 50 nm. Therefore, a source resistance and a drain resistance increase and hence transistor characteristics are deteriorated.
As a method of reducing the source resistance and the drain resistance, for example, a salicide process for depositing a high melting-point metal like titanium or cobalt on a source/drain region and selectively forming a metal silicide layer by heat treatment has been used.
Since, however, the thickness of the SOI layer is thinned to about 20 nm to about 50 nm as described above and consequently the amount of silicon per se consumed by reaction with the high melting-point metal upon the salicide process falls short, the aggregation of metal silicide occurs and hence a metal silicide-free portion, i.e., a concave portion is yielded. When a contact hole is defined in such a form that the concave portion and the contact hole are brought into alignment with each other, the concave portion will cause a fault in that etching is not successfully stopped at the concave portion, and a buried oxide film placed under the silicide layer is also etched. If even the buried oxide film is etched, then a silicon substrate and each wiring are short-circuited to thereby cause a defect important to the SOI device. Such a fault will increase along with the thinning of the SOI layer with accelerating speed.